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symbol pin name a0~a15 address input q0~q7 data input/output ce chip enable input oe output enable input vpp program supply voltage nc no internal connection vcc power supply pin (+5v) gnd ground pin features ? 64k x 8 organization ? +5v operating power supply ? +12.75v program/erase voltage ? electric erase instead of uv light erase ? fast access time: 70/90/100/120/150 ns ? totally static operation ? completely ttl compatible 1 ? operating current: 30ma ? standby current: 100ua ? 100 minimum erase/program cycles ? package type: - 28 pin plastic dip - 28 pin sop - 32 pin plcc - 28 pin tsop(i) rev.1.8, jul. 13 , 1998 p/n: pm0455 patent#: us#5,523,307 pin configurations pdip/sop pin description the MX26C512A supports an intelligent quick pulse programming algorithm which can result in a program- ming time of less than 30 seconds. this mtp eprom tm is packaged in industry standard 28 pin dual-in-line packages, 32 pin plcc packages or 28 pin tsop packages and 28 pin sop packages. plcc block diagram tsop general description the MX26C512A is a 12.75v/5v, 512k-bit, mtp eprom tm (multiple time programmable read only memory). it is organized as 64k words by 8 bits per word, operates from a + 5 volt supply, has a static standby mode, and features fast single address location program- ming. it is designed to be reprogrammed and erased by an eprom programmer or on-board. all programming/ erasing signals are ttl levels, requiring a single pulse. MX26C512A 512k-bit [64k x 8] cmos multiple-time-programmable eprom control logic output buffers q0~q7 ce oe a0~a15 address inputs y-decoder x-decoder y-select 512k bit cell maxtrix vcc gnd vpp . . . . . . . . . . . . . . . . MX26C512A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vcc a14 a13 a8 a9 a11 oe/vpp a10 ce q7 q6 q5 q4 q3 1 4 5 9 13 14 17 20 21 25 29 32 30 a8 a9 a11 nc oe/vpp a10 ce q7 q6 a6 a5 a4 a3 a2 a1 a0 nc q0 q1 q2 gnd nc q3 q4 q5 a7 a12 a15 nc vcc a14 a13 MX26C512A oe/vpp a11 a9 a8 a13 a14 vcc a15 a12 a7 a6 a5 a4 a3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 a10 ce q7 q6 q5 q4 q3 gnd q2 q1 q0 a0 a1 a2 21 20 19 18 17 16 15 14 13 12 11 10 9 8 MX26C512A patented technology
2 rev.1.8, jul. 13 , 1998 p/n: pm0455 patent#: us#5,523,307 MX26C512A functional description when the MX26C512A is delivered, or it is erased, the chip has all 512k bits in the "one", or high state. "zeros" are loaded into the mx26c512 through the procedure of programming. programming mode programmming algorithm the MX26C512A is programmed by an eprom programmer or on-board. the device is set up in the programming mode when the programming voltage oe/ vpp = 12.75v is applied, with vcc = 5 v (algorithm shown in figure 1). programming is achieved by applying a single ttl low level 25us pulse to the ce input after addresses and data lines are stable. if the data is not verified, additional pulses are applied for a maximum of 20 pulses. after the data is verified, one 25us pulse is applied to overprogram the byte so that program margin is assured. this process is repeated while sequencing through each address of the device. when programming is completed, the data at all the addresses are verified at vcc = 5v 10%. the vcc supply of the mxic on-board programming algorithm is designed to be 5v 10% particularly to facilitate the programming operation under the on-board application environment. but it can also be implemented in an industrial-standard eprom programmer. compatibility with mx27c512 fast programming algorithm besides the on-board programming algorithm, the fast programming algorithm of mx27c512 also applies to MX26C512A. mxic fast algorithm is the conventional eprom programing algorithm and is available in industrial-standard eprom programmers. a user of industrial-standard eprom programmer can choose either of the algorithms base on his preference. the device is set up in the fast programming mode when the programming voltage oe/vpp = 12.75v isapplied, with vcc = 6.25v, (algorithm is shown in figure 2). the programming is achieved by appling a single ttl low level 25~100us pulse to the ce input after addresses and data line are stable. if the data is not verified, an additional pulse is applied for a maximum of 25 pulses. this process is repeated while sequencing through each address of the device. when the programming mode is completed, the data in all address is verified at vcc = 5v 10%. erase mode the MX26C512A is erased by eprom programmer or in-system. the device is set up in erase mode when a9 =oe/vpp = 12.75v are applied, with vcc = 5v. (algorithm is shown in figure 3). the erase time is around 1sec. if the erase is not verified, an additional erase processes will be repeated for a maximum of 200 times. program inhibit mode programming of multiple MX26C512A in parallel with different data is also easily accomplished by using the program inhibit mode. except for ce and oe, all like inputs of the parallel mx26c512 may be common. a ttl low-level program pulse applied to an MX26C512A ce input with oe/vpp = 12.75 0.25 v will program that MX26C512A. a high-level ce input inhibits the other MX26C512A from being programmed. program verify mode verification should be performed on the programmed bits to determine that they were correctly programmed. the verification should be performed with oe/vpp and ce, at vil. data should be verified tdv after the falling edge of ce. erase verify mode verification should be performed on the erased chip to determine that whole chip(all bits) was correctly erased. verification should be performed with oe/vpp and ce at vil and vcc = 5v. auto identify mode the auto identify mode allows the reading out of a binary code from a mtp that will identify its manufacturer and device type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional in the 25 c 5 c ambient temperature range that is required when programming the MX26C512A. to activate this mode, the programming equipment must force 12.75v on address line a9 of the device. two identifier bytes may then be sequenced from the device outputs by toggling address line a0 from vil to vih. all
3 rev.1.8, jul. 13 , 1998 p/n: pm0455 patent#: us#5,523,307 MX26C512A other address lines must be held at vil during auto identify mode. byte 0 ( a0 = vil) represents the manufacturer code, and byte 1 (a0 = vih), the device identifier code. for the MX26C512A, these two identifier bytes are given in the mode select table. all identifiers for the manufacturer and device codes will possess odd parity, with the msb (dq7) defined as the parity bit. read mode the MX26C512A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. chip enable (ce) is the power control and should be used for device selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that addresses are stable, address access time (tacc) is equal to the delay from ce to output (tce). data is available at the outputs toe after the falling edge of oe, assuming that ce has been low and addresses have been stable for at least tacc - toe. standby mode the MX26C512A has a cmos standby mode which reduces the maximum vcc current to 100 ua. it is placed in cmos standby when ce is at vcc 0.3 v. the MX26C512A also has a ttl-standby mode which reduces the maximum vcc current to 1.5 ma. it is placed in ttl-standby when ce is at vih. when in standby mode, the outputs are in a high-impedance state, independent of the oe input. two-line output control function to accommodate multiple memory connections, a two- line control function is provided to allow for: 1. low memory power dissipation, 2. assurance that output bus contention will not occur. it is recommended that ce be decoded and used as the primary device-selecting function, while oe be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. system considerations during the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of chip enable. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. at a minimum, a 0.1 uf ceramic capacitor (high frequency, low inherent inductance) should be used on each device between vcc and gnd to minimize transient effects. in addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on eprom arrays, a 4.7 uf bulk electrolytic capacitor should be used between vcc and gnd for each of the eight devices. the location of the capacitor should be close to where the power supply is connected to the array.
4 rev.1.8, jul. 13 , 1998 p/n: pm0455 patent#: us#5,523,307 MX26C512A figure 1. programming flow chart notes: 1. vh = 12.0v 0.5v 2. x = either vih or vil(for auto select) 3. a1 - a8 = a10 - a15 = vil(for auto select) 4. see dc programming characteristics for vpp voltage during programming. mode select table pins mode ce oe/vpp a0 a9 outputs read vil vil x x dout output disable vil vih x x high z standby (ttl) vih x x x high z standby (cmos) vcc x x x high z program vil vpp x x din program verify vil vil x x dout erase vil vpp x vpp high z erase verify vil vil x x dout program inhibit vih x x x high z manufacturer code vil vil vil vh c2h device code(26c512) vil vil vih vh d1h start address = first location vcc = 5v vpp = 12.75v x = 0 program one 25us pulse increment x x = 20 ? verify byte last address vcc = 5v vpp = vil verify all bytes ? device failed increment address interactive section verify section fail yes pass no yes no fail fail ? program one 25us pulse program one 25us pulse device passed pass
5 rev.1.8, jul. 13 , 1998 p/n: pm0455 patent#: us#5,523,307 MX26C512A figure 2. compatibility with mx27c512 fast programming flow chart start address = first location vcc = 6.25v oe/vpp = 12.75v program one 25~100us pulse x = 0 last address ? verify byte vcc = 5.0v device passed compare all bytes to original data device failed increment address fail pass no no yes yes address = first location last address ? increment address fail pass increment x x = 25 ? no oe/vpp = vil yes program one 25~100us pulse
6 rev.1.8, jul. 13 , 1998 p/n: pm0455 patent#: us#5,523,307 MX26C512A figure 3. erasing mode flow chart start x = 0 program all "0" a9 = 12.75v vcc = 5v vpp = 12.75v chip erase (0.5s) erase verify ? yes no device passed a9 = vil or vih vcc = 5v oe/vpp = vil x = 200 ? device failed increment x pass fail all bits verify chip erase (0.5s)
7 rev.1.8, jul. 13 , 1998 p/n: pm0455 patent#: us#5,523,307 MX26C512A switching test circuits switching test waveforms device under test diodes = in3064 or equivalent cl = 100 pf including jig capacitance(30pf for 70 ns parts) 6.2k ohm 1.8k ohm +5v cl 3.0v 0v test points input output ac testing: (1) inputs are driven at 3.0v for a logic "1" and 0v for a logic "0". input pulse rise and fall times are < 10ns. 1.5v (2) for MX26C512A 1.5v
8 rev.1.8, jul. 13 , 1998 p/n: pm0455 patent#: us#5,523,307 MX26C512A symbol parameter min. max. unit conditions voh output high voltage 2.4 v ioh = -0.4ma vol output low voltage 0.4 v iol = 2.1ma vih input high voltage 2.0 vcc + 0.5 v vil input low voltage -0.3 0.8 v ili input leakage current -10 10 ua vin = 0 to 5.5v ilo output leakage current -10 10 ua vout = 0 to 5.5v icc3 vcc power-down current 100 ua ce = vcc 0.3v icc2 vcc standby current 1.5 ma ce = vih icc1 vcc active current 30 ma ce = vil, f=5mhz, iout = 0ma notice: stresses greater than those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. notice: specifications contained within the following tables are subject to change. dc characteristics ta = 0 o c to 70 o c, vcc = 5v 10% absolute maximum ratings rating value ambient operating temperature 0 o c to 70 o c storage temperature -65 o c to 125 o c applied input voltage -0.5v to 7.0v applied output voltage -0.5v to vcc + 0.5v vcc to ground potential -0.5v to 7.0v a9 & vpp -0.5v to 13.5v capacitance ta = 25 o c, f = 1.0 mhz (sampled only) symbol parameter typ. max. unit conditions cin input capacitance 8 8 pf vin = 0v cout output capacitance 8 12 pf vout = 0v cvpp vpp capacitance 18 25 pf vpp = 0v
9 rev.1.8, jul. 13 , 1998 p/n: pm0455 patent#: us#5,523,307 MX26C512A 26c512a 26c512a -70 -90 symbol parameter min. max. min. max. unit conditions tacc address to output delay 70 90 ns ce = oe = vil tce chip enable to output delay 70 90 ns oe = vil toe output enable to output delay 35 40 ns ce = vil tdf oe high to output float, 0 20 0 25 ns or ce high to output float toh output hold from address, 0 0 ns ce or oe which ever occurred firs 26c512a 26c512a 26c512a -10 -12 -15 symbol parameter min. max. min. max. min. max. unit conditions tacc address to output delay 100 120 150 ns ce = oe = vil tce chip enable to output delay 100 120 150 ns oe = vil toe output enable to output delay 45 50 65 ns ce = vil tdf oe high to output float, 0 30 0 35 0 50 ns or ce high to output float toh output hold from address, 0 0 0 ns ce or oe which ever occurred first ac characteristics ta = 0 o c to 70 o c, vcc = 5v 10% dc programming characteristics ta = 25 o c 5 o c symbol parameter min. max. unit conditions voh output high voltage 2.4 v ioh = -0.40ma vol output low voltage 0.4 v iol = 2.1ma vih input high voltage 2.0 vcc + 0.5 v vil input low voltage -0.3 0.8 v ili input leakage current -10 10 ua vin = 0 to 5.5v vh a9 auto select voltage 11.5 12.5 v icc3 vcc supply current (program/erase & verify) 50 ma ipp2 vpp supply current(program)/erase 50 ma ce = pgm = vil, oe = vih vcc2 programming & erase supply voltage 4.5 6.5 v vpp2 programming & erase voltage 12.5 13.0 v ipp a9 a9 auto select current /erase 1 ma ce = pgm = vil, oe = vih
10 rev.1.8, jul. 13 , 1998 p/n: pm0455 patent#: us#5,523,307 MX26C512A ac programming characteristics ta = 25 o c 5 o c symbol parameter min. max. unit conditions tas address setup time 2.0 us toes oe setup time 2.0 us tds data setup time 2.0 us tah address hold time 0 us tdh data hold time 2.0 us tdfp ce to output float delay 0 130 ns tvps vpp setup time 2.0 us tpw program pulse width 20 105 us tvcs vcc setup time 2.0 us tdv data valid from ce 250 ns tces ce setup time 2.0 us toe data valid from oe 150 ns ter erase recovery time 0.5 s tew erase pulse width 0.5 s tev erase verify time 200 ns tpv program verify time 200 ns ta9s a9 setup time 2.0 us tpvs program verify setup 2 us tevs erase verify setup 0.5 s waveforms read cycle address inputs data out oe ce data address valid data tdf tacc tce toe tdh
11 rev.1.8, jul. 13 , 1998 p/n: pm0455 patent#: us#5,523,307 MX26C512A erase waveforms programming waveforms address ce oe/vpp a9 vil vpp vil vih vil tces others not care out erase erase verify ter tev vih tew tvps tevs out vpp addresses vih vil vcc vcc1 vcc ce vih vil program program verify tpw tprt tds tvps tvcs tas tdh tpr tpvs tpv tah tdfp tdv data oe/vpp vpp1 vil
12 rev.1.8, jul. 13 , 1998 p/n: pm0455 patent#: us#5,523,307 MX26C512A plastic package part no. access time(ns) operating current max.(ma) standby current max.(ua) package MX26C512Apc-70 70 30 100 28 pin dip MX26C512Amc-70 70 30 100 28 pin sop MX26C512Aqc-70 70 30 100 32 pin plcc MX26C512Atc-70 70 30 100 28 pin tsop(i) MX26C512Apc-90 90 30 100 28 pin dip MX26C512Amc-90 90 30 100 28 pin sop MX26C512Aqc-90 90 30 100 32 pin plcc MX26C512Atc-90 90 30 100 28 pin tsop(i) MX26C512Apc-10 100 30 100 28 pin dip MX26C512Amc-10 100 30 100 28 pin sop MX26C512Aqc-10 100 30 100 32 pin plcc MX26C512Atc-10 100 30 100 28 pin tsop(i) MX26C512Apc-12 120 30 100 28 pin dip MX26C512Amc-12 120 30 100 28 pin sop MX26C512Aqc-12 120 30 100 32 pin plcc MX26C512Atc-12 120 30 100 28 pin tsop(i) MX26C512Apc-15 150 30 100 28 pin dip MX26C512Amc-15 150 30 100 28 pin sop MX26C512Aqc-15 150 30 100 32 pin plcc MX26C512Ac-15 150 30 100 28 pin tsop(i) ordering information
13 rev.1.8, jul. 13 , 1998 p/n: pm0455 patent#: us#5,523,307 MX26C512A 28-pin plastic dip (600 mil) 32-pin plastic leaded chip carrier (plcc) note: each lead centerline is located within .25 mm[.01 inch] of its true position [tp] at maximum material condition. note: each lead centerline is located within .25 mm[.01 inch] of its true position [tp] at maximum material condition. package information item millimeters inches a 37.34 max 1.470 max b 2.03 [ref] .080 [ref] c 2.54 [tp] .100 [tp] d .46 [typ.] .018 [typ.] e 32.99 1.300 f 1.52 [typ.] .060 [typ.] g 3.30 .25 .130 .010 h .51 [ref] .020 [ref] i 3.94 .25 .155 .010 j 5.33 max. .210 max. k 15.22 .25 .600 .010 l 13.84 .25 .545 .010 m .25 [typ.] .010 [typ.] item millimeters inches a 12.44 .13 .490 .005 b 11.50 .13 .453 .005 c 14.04 .13 .553 .005 d 14.98 .13 .590 .005 e 1.93 .076 f 3.30 .25 .130 .010 g 2.03 .13 .080 .005 h .51 .13 .020 .005 i 1.27 [typ.] .050 [typ.] j .71[ref] .028[ref] k .46 [ref] .018 [ref] l 10.40/12.94 .410/.510 (w) (l) (w) (l) m .89 r .035 r n .25 (typ.) .010 (typ.) ij hg b c f d e a 1 14 k l m 0~15? 15 28 1 b a 4 5 9 13 14 17 20 21 25 29 32 cd e f g h i k j l m n 30
14 rev.1.8, jul. 13 , 1998 p/n: pm0455 patent#: us#5,523,307 MX26C512A 28-pin plastic tsop note: each lead centerline is located within .25 mm of its true position [tp] at maximum material condition. note: each lead centerline is located within .25 mm[.01 inch] of its true position [tp] at maximum material condition. item millimeters a 13.4 .2 b 11.8 .1 c 8.0 .1 d .15 .01 f .2 .03 h .55 [typ.] i .425 [typ.] j .05 [min.] k 1.00 .05 l 1.25 [max.] m .05 .20 no ~ 5 28-pin plastic sop(330 mil) item millimeters inches a 18.62 max. .733 max. b 1.194 max .047 max c 1.27 [tp] .050 [tp] d .41 [typ.] .016 [typ.] e .10 min. .004 min. f 2.85 max. .110 max. g 2.49 .13 .098 .005 h 11.81 .31 .465 .012 i 8.41 .13 .331 .005 j 1.70 .20 .067 .008 k .25 [typ.] .010 [typ.] l .91 .20 .036 .008 a b c d e f g h i j kl m n 114 15 28 a dc b e gf l k j i h
15 rev.1.8, jul. 13 , 1998 p/n: pm0455 patent#: us#5,523,307 MX26C512A revision history revision# description date 1.2 add 28 pin tsop and sop packages. 3/28/1997 1.3 erasing mode flow chart: chip erase (5s)----> (1s). 4/10/1997 programming waveforms: ce changed. 1.4 mtp rom--->mtp eprom 5/30/1997 chip erase(1s)--->0.5s. x = 60?--->200? switching test waveforms revise. tew erase pulse width 1 sec---> 0.5 sec. programming/erase waveforms modifiction. vpp:from 12.0~13v to 12.5v ~13v. 1.5 erase verify time: 60 ---->200. 7/25/1997 1.6 change part name: 26c512 ---> 26c512a 11/05/1997 1.7 change tpw:min. 95us -->min. 20us. 2/10/1998 programming flow chart revised. mode select table, erase mode a9=vh-->a9=vpp. erase flow chart revised. 1.8 delete ipp in dc characteristics 7/13/1998
16 MX26C512A m acronix i nternational c o., l td. headquarters: tel:+886-3-578-8888 fax:+886-3-578-8887 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-747-2309 fax:+65-748-4090 taipei office: tel:+886-3-509-3300 fax:+886-3-509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the rignt to change product and specifications without notice.

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